1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly to a pattern of a plurality of interconnection lines connected to each other by a plurality of via or contact plugs in a semiconductor integrated circuit device provided with a redundancy layout design.
2. Description of the Related Art
In semiconductor integrated circuit devices (LSI) having high integration degrees, generation change or progress requires design rules for realizing designs with smaller pattern shapes. However, with a decrease in the size of pattern shapes, the number of defects is increased due to accidental factors and process fluctuations caused in the manufacturing process. In order to prepare for occurrence of such defects and thereby to improve the yield rate, pattern layout designs are arranged to employ a redundant structure dispensable for the operation, as a defect countermeasure.
In this respect, Jpn. Pat. Appln. KOKAI Publication No. 2001-284455 discloses the following technique. Specifically, via regions respective formed on the layers of interconnection lines are set to have essentially the same width as the line width of the respective interconnection layers. Where a via hole is formed at an end of an interconnection line, this via hole is elongated beyond the end of the interconnection line by a predetermined length in the length direction of the interconnection line. Consequently, it is possible to suppress problems in relation to minimum areas and/or the end of lines.